The present invention relates to a pattern formation method for use in fabrication processing or the like for a semiconductor integrated circuit device.
In the fabrication processing for a semiconductor integrated circuit device or the like, the size of a resist pattern (pattern width) formed by lithography technique is further refined in accordance with increase in the degree of integration of semiconductor integrated circuits, and accordingly, the aspect ratio of a resist pattern is remarkably increasing.
Also, the dielectric constant of an insulating film is desired to be further lowered in accordance with improved performance of semiconductor devices. Therefore, use of a low dielectric insulating film that has a lower dielectric constant than a generally used silicon oxide film, such as an insulating film having pores or including an organic material, has been proposed.
Now, a conventional pattern formation method will be described with reference to FIGS. 6A through 6D.
First, a chemically amplified resist material having the following composition is prepared:
Base polymer: poly((methoxymethyl acrylate) − (γ-butyrolactone  2 gmethacrylate)) (wherein methoxymethyl acrylate:γ-butyrolactonemethacrylate = 70 mol %:30 mol %)Acid generator: triphenylsulfonium triflate0.04 gSolvent: propylene glycol monomethyl ether acetate  20 g
Next, an organic polymer made of aromatic hydrocarbon including no fluorine (for example, SiLK manufactured by Hitachi Chemical Co., Ltd. (with a dielectric constant of 2.65)) is deposited on a substrate 1 so as to form a low dielectric insulating film 2. Thereafter, the chemically amplified resist material having the aforementioned composition is applied on the low dielectric film 2, and then, the resultant substrate 1 is annealed with a hot plate (not shown) at a temperature of 90° C. for 60 seconds. Thus, a resist film 3 with a thickness of 0.4 μm is formed.
Next, as shown in FIG. 6B, pattern exposure is carried out by irradiating the resist film 3 with ArF excimer laser 5 through a photomask 4 having a desired pattern.
Then, as shown in FIG. 6C, the resist film 3 is subjected to post-exposure bake (PEB) by annealing the substrate 1 with a hot plate (not shown) at a temperature of 105° C. for 90 seconds. Thus, an exposed portion 3a of the resist film 3 becomes soluble in an alkaline developer because an acid is generated from the acid generator therein while an unexposed portion 3b of the resist film 3 remains insoluble in an alkaline developer because no acid is generated from the acid generator therein.
Next, after the pattern exposure, the resist film 3 is developed with an alkaline developer of a 2.38 wt % tetramethylammonium hydroxide aqueous solution for 60 seconds and is then rinsed with pure water for 60 seconds. Thereafter, the resultant resist film 3 is dried. Thus, a resist pattern 6 with a pattern width of 0.11 μm is formed from the unexposed portion 3b of the resist film 3 as shown in FIG. 6D.
The cross-sectional shape of the resist pattern 6 has, however, a footing shape as shown in FIG. 6D, and thus, the pattern shape is defective.
The conventional pattern formation method shown in FIGS. 6A through 6D is employed for forming a positive resist pattern 6. In the case where a negative resist pattern is formed, the resultant resist pattern has an undercut cross-sectional shape, and the pattern shape is also defective.
When a resist pattern in a defective pattern shape is used for etching a film to be etched, the shape of the resultant pattern of the etched film is also defective, which disadvantageously lowers the yield of semiconductor devices.